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| Beyond Innovation Technology Co., Ltd. www..com BIT3102A BIT3102A Low Cost PWM CCFL Controller Version:A0 Please read the notice stated in this preamble carefully before accessing any contents of the document attached. Admission of BiTEK's statement therein is presumed once the BiTEK document is released to the receiver. May 16, 2007 DCC CONTROLLED 2006/07/04 Confidential, for authorized user only page 1 of 7 DOC NO.W-DS-0020 Beyond Innovation Technology Co., Ltd. www..com BIT3102A Notice: Firstly, the information furnished by Beyond Innovation Technology Co. Ltd. (BiTEK) in this document is believed to be accurate and reliable and subject to BiTEK's amendment without prior notice. And the aforesaid information does not form any part or parts of any quotation or contract between BiTEK and the information receiver. Further, no responsibility is assumed for the usage of the aforesaid information. BiTEK makes no representation that the interconnect of its circuits as described herein will not infringe on exiting or future patent rights, nor do the descriptions contained herein imply the granting of licenses to make, use or sell equipment constructed in accordance therewith. Besides, the product in this document is not designed for use in life support appliances, devices, or systems where malfunction of this product can reasonably be expected to result in personal injury. BiTEK customers' using or selling this product for use in such applications shall do so at their own risk and agree to fully indemnify BiTEK for any damage resulting from such improper use or sale. At last, the information furnished in this document is the property of BiTEK and shall be treated as highly confidentiality; any kind of distribution, disclosure, copying, transformation or use of whole or parts of this document without duly authorization from BiTEK by prior written consent is strictly prohibited. The receiver shall fully compensate BiTEK without any reservation for any losses thereof due to its violation of BiTEK's confidential request. The receiver is deemed to agree on BiTEK's confidential request therein suppose that said receiver receives this document without making any expressly opposition. In the condition that aforesaid opposition is made, the receiver shall return this document to BiTEK immediately without any delay. -Version A4 BiTEK May 16, 2007 DCC CONTROLLED 2006/07/04 Confidential, for authorized user only page 2 of 7 DOC NO.W-DS-0020 Beyond Innovation Technology Co., Ltd. BIT3102A Pin Layout: OUT VDD CMP VIN1 8 GND RT SST OLP 5 Features: www..com PWM Modulation Open Lamp Protection Internal UVLO (Under Voltage Lock Out) function Dimming Control CMOS Totem Pole output NMOS output driving SOP /DIP Packing 4 Applications: Cold Cathode Fluorescent Lamps system Notebook PC LCD Monitor Palm-top Computers Video Phone/ Door Phone Portable Instrumentation Personal Digital Assistants Airline Entertainment Centers Automotive Display ATM/ Financial Terminal POS Terminal Navigation Devices (GPS Equipment) Test Equipment Copiers and Office Equipment Medical Equipment General Description: To aim at the Cold Cathode Fluorescent Lamp (CCFL) applications, the BIT3102A integrated all functions required in a single 8 pin chip. The chip provides a fully functioned PWM control circuit with a true lamp current feedback protection. By setting the required time for striking the lamp through SST , the open-lamp condition can be detected after lamp striking period. The lamp dimming can be done through a PWM feedback loop. CMOS process reduces the operating current (1mA typical) and NMOS output driving capability enhances the system efficiency. Absolute Ratings: (if Ta=25) VDD.......................................-0.3 ~ +9.0 V GND.......................................0.3 V Input Voltage.............................-0.3 ~ VDD+0.3 V Operating Ambit Temperature.......0 ~ +70 Operating Junction Temperature....+150 Storage Temperature...................-55~+150 Recommended Operating Condition: Supply Voltage..................................4.5 ~ 8.5 V Operating Frequency..........................50K ~ 250K Hz Operating Ambient Temperature............0 ~ 70 Functional Block Diagram: VDD= 4.5 ~ 13.2V OUT GND 11 Current Mirror VDD VDD UVLO 4.0V 2.25V 0.75V 2.15V 3.8V ISS + - VDD 2.25V Ramp Wave Generator - 0.75V Band Gap Reference 2.5V - RT Error Amplifier + - 1.5V 325mV - VDD + BiTEK SST VDD CMP VIN- 2006/07/04 Confidential, for authorized user only + Latch + May 16, 2007 DCC CONTROLLED OLP page 3 of 7 DOC NO.W-DS-0020 Beyond Innovation Technology Co., Ltd. BIT3102A VSST = ISSRSS (1-e ); (Fig.a) Where ISS= VRT/RT 15%,and VRT =2.15V The output is disabled to "low" level and open lamp protection is disable while SST <0.325V. A ~ 180uA current is flow into INN to set the initial state. The PWM BI3102 RT controller is enable while 2.5V < SST < 0.325V. The open lamp protection circuit SST will be enable when VSST > 2.5V (Fig.b) The required time for striking Fig.a RT Rss Css 11 Current Mirror VDD VDD Function Description: www..com Fig.b Table 1. Power On Initialization and Open Lamp Protection OUT Disable to "Low" Enable Enable OLP Disable Disable Enable VINInternally Forced to "High" Externally Controlled Externally Controlled SST < 0.325V 2.5V < SST < 0.325V SST >2.5V Pin Description: Pin No. 1 2 3 4 5 6 7 8 Names OUT VDD CMP VinOLP SST RT GND Description PWM output, logic high active for driving NMOS device. Supply voltage. PWM controller input, the output of error amplifier. PWM controller input, the inverting input of error amplifier. A voltage sense input pin. If voltage level is less than 325 mV after a user defined period of time, the chip will shut down the OUT and PWM circuits. A digital latch circuit latches this result. The latch condition will be released if the power be turned off. The timer for open lamp protection. Operation frequency control. Ground DC/AC Characteristics: Parameter Reference Voltage Output voltage Line regulation 2006/07/04 Measure VinVDD=6.0V, Ta=25C VDD=4.5 ~ 8.5 V Confidential, for authorized user only 1.455 Test Conditions Min. - + UVLO: The Under-Voltage-Lock-Out circuit turns the output driver off when supplying voltage drops to a specified low level. Band Gap Reference: This circuit provides a accuracy voltage reference which is very stable even though the operating temperature is variable. Base on this reference, a specified voltage can be generated which is used by another circuit. Ramp Wave Generator: This circuit generates a typical 140KHz ramp wave. (as RT =100 K) The relation between frequency and resistor RT is as the equation below: Freq. (KHz) = 14000/RT(K) PWM Controller: The pulse width modulation control circuit includes a ramp wave generator, an error amplifier and a comparator. These devices provide the required active components for the PWM feedback control application. The Power On Initialization and Open Lamp Protection: The current source ISS charges the external resistor and capacitor during power on process. The voltage drops on the SST pin will be increased as -t/RssCss ISS 2.15V1.5V + - RT Opan Lamp Enable 2V the lamp could be calculated as bellow: TSTRIKE = (RSSCSS) ln((ISSRSS-0.325)/(ISSRSS-2.5)) TSTRIKE is decided by the characteristic of lamp. 2.5V SST Typ.(Limits) BiTEK Max. May 16, 2007Unit 1.545 20 V DCC CONTROLLED 2 mV page 4 of 7 1.5 DOC NO.W-DS-0020 Beyond Innovation Technology Co., Ltd. Under Voltage Lock Out www..com Upper threshold voltage Hysteresis Ramp Wave Generator Frequency Operating Frequency Output peak Output valley Error Amplifier Input voltage Open loop gain Unit gain band width Open Lamp Enable Output current Open lamp detection enable Open Lamp Protection Open lamp detection lower threshold Hysteresis Output CMOS output impedance Rising Time Falling Time note 1 1000pF load, note 1 50 110 100 VDD=6.0V, Ta=25 325 50 VDD=6.0V, Ta=25 2.15V/RT 2.5 note 1 0.75 60 1 80 1.5 RT=100K note 1 120 50 2.25 0.75 140 Ta=25 3.8 0.1 4 0.2 BIT3102A 4.2 0.3 160 250 V V KHz KHz V V 2.25 V dB MHz uA V mV mV ns ns Ta : ambient temperature. Note 1: It is guaranteed by design not 100% tested. Application Circuit: A low cost 1~2 lamp design. CN2 HV LV BIT3102A CN1 VDD BRIGHTNESS GND 1 2 3 1 2 3 4 OUT GND VDD RT CMP SST VIN- OLP 8 7 6 5 VDD=4.5V~13.2V BRIGHTNESS=DC 0~3.3V, 0V brightest dimming. CN2 may connect 1~2 CCFLs BiTEK May 16, 2007 DCC CONTROLLED page 5 of 7 2006/07/04 Confidential, for authorized user only DOC NO.W-DS-0020 Beyond Innovation Technology Co., Ltd. BIT3102A Layout Notice: www..com Note 1. Please keep the capacitor between VDD and GND as close as possible. Noisy IC VDD may trigger UVLO or causes EOS (Electrical Over Stress). Fig. D is an example of making shortest traces between VDD and GND. The layout traces are under the IC. OUT VDD CMP VIN- 1 8 GND RT SST OLP 5 4 Fig. D Order Information: BIT3102A-SO SOP type packing Part number Beyond Innovation Technology Co., Ltd. BIT3102A-DP DIP type packing Part number Beyond Innovation Technology Co., Ltd. BiTEK May 16, 2007 DCC CONTROLLED 2006/07/04 Confidential, for authorized user only page 6 of 7 DOC NO.W-DS-0020 Beyond Innovation Technology Co., Ltd. www..com Package Information : BIT3102A Unit: mm SOP type : DIP type : BiTEK May 16, 2007 DCC CONTROLLED 2006/07/04 Confidential, for authorized user only page 7 of 7 DOC NO.W-DS-0020 |
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